The present invention relates to a method of connecting wirings through a connection hole.
Recently, as the packing density of LSIs is increased, a demand has arisen for a smaller contact hole for connecting a semiconductor substrate with a wiring layer or a smaller through hole for connecting a lower wiring with an upper wiring (such a contact hole and a through hole are called connection holes). Meanwhile, an insulating interlayer for insulating the upper wiring from the lower wiring cannot be formed thinner than a predetermined thickness in order to prevent dielectric breakdown and therefore must normally have a thickness of about 0.5 m or more. Therefore, an aspect ratio (connection hole depth/connection hole diameter) of a connection hole has been increased.
In addition, in order to arrange elements with high packing density, multi-layered wirings of two or more layers must be formed. Therefore, in order to form fine multi-layered wirings with high accuracy, the surface of the insulating interlayer must be flattened. In this case, a variety of elements are formed on the surface of a semiconductor substrate and hence the surface normally has undulations. Therefore, if the insulating interlayer is formed flat on the surface and connection holes are formed therein, the depths of the connection holes become different in correspondence to the underlying undulations.
For this reason, the manufacturing yield and reliability of the fine multi-layered wirings are degraded mainly by (1) an increase in the aspect ratio and (2) the presence of the contact holes having different depths.
That is, a wiring layer is normally formed by depositing a metal such as Al and Mo on the entire surface of a substrate by sputtering and then performing lithography and etching. However, if a side wall of a connection hole is vertical, a burying rate (deposited film thickness in connection hole/deposited film thickness on flat surface) is abruptly reduced when the aspect ratio is increased close to 1, as shown in FIG. 9. Therefore, if the insulating interlayer cannot be formed thin, a metal cannot be sufficiently deposited in a connection hole when a connection hole diameter becomes smaller than a predetermined value, thereby disconnecting the wiring layer.
In order to solve the above problem, a method of tapering a side wall of a connection hole is proposed.
A simplest tapering method is a method of opening a connection hole by wet etching. This method will be described with reference to FIGS. 10A to 10C wherein through holes are formed.
In FIG. 10A, an Al wiring 2 is formed on a semiconductor substrate 1 having a step la on its surface, and an SiO.sub.2 layer 3 having a flat surface is formed thereon by a known bias sputtering method or etch-back method.
In FIG. 10B, a resist layer 7 is patterned by normal lithography to form a contact hole pattern. In FIG. 10C, through holes 4 and 4' having different depths are formed by wet etching using a buffer hydrofluoric acid solution are the resist layer 7 as an etching mask. As is apparent from the shape of the through hole 4, since wet etching is isotropic etching, a taper angle 5 is about 45.degree. . Therefore, a pattern conversion difference (a pattern size difference between a resist layer 7 and an SiO.sub.2 layer 3) becomes about twice a depth on an upper surface of the through hole.
Meanwhile, since the shallow through hole 4' is dipped in the etching solution until the deep through hole 4 is formed, the pattern conversion difference is increased even on the bottom surface of the through hole. In addition, in wet etching, the etching rate largely varies in a wafer. Therefore, in order to completely form through holes on the entire wafer surface, overetching must be performed. As a result, the conversion difference is further increased.
Another method of tapering a side wall of a connection hole is a method utilizing reactive ion etching (RIE) as dry etching. An example of this method is disclosed in Japanese Patent Laid-Open No. 58-93237. In this case, a substrate is processed following the same procedures as in FIGS. 10A and 10B, and then the SiO.sub.2 layer 3 is etched by anisotropic etching as shown in FIG. 10D. After connection holes 4 and 4' having substantially vertical side walls are formed, the resist 7 is removed, and then RIE is performed on the entire surface using a gas mixture of C.sub.3 F.sub.8 and H.sub.2. In this case, if conditions are selected such that a polymer is deposited on a flat portion and etching progresses at upper end corner portions of the connection holes, etching is not performed on portions other than the connection holes, and therefore only the connection holes are tapered as shown in FIG. 10E. However, in this method, since polymerization and etching are used at the same time, the following problems are posed.
That is, in this method, characteristics of polymerization and etching largely depend on environments. More specifically, conditions of polymerization are changed in accordance with the type of an apparatus, the history of an apparatus, a loading effect, the size and the density of a pattern, and the like. For this reason, a complex process is required to set the conditions, and uniformity and reproducibility are degraded.
In addition, since the polymer is deposited on the flat surface, contamination caused by carbon (C) or the like may occur.
Therefore, using the above conventional methods, a side wall of a connection hole cannot be tapered at an arbitrary angle and the pattern conversion difference on the connection hole bottom surface cannot be eliminated. Even if these conditions are satisfied, a semiconductor device having a high manufacturing yield and reliability cannot be obtained.
In order to prevent disconnection of a wiring layer, a selective growth method of tungsten (W) is proposed.
This method utilizes a reaction in which tungsten is grown on only a conductive layer but not grown on an insulating layer in a certain gas atmosphere within a certain temperature range. The gas atmosphere is obtained by a gas mixture of WF.sub.6 and H.sub.2, and the temperature is normally about 300.degree. C. Manufacturing steps of this selective growth method used to bury a contact hole will be described below with reference to FIGS. 11A to 11D.
In FIG. 11A, an SiO.sub.2 layer 2 is formed on an Si (silicon) substrate 1 by a normal CVD or sputtering method. Then, as shown in FIG. 11B, a connection hole 4 is formed in the SiO.sub.2 layer 2 by lithography and etching. Thereafter, as shown in FIG. 11C, tungsten 14 is selectively grown in the connection hole 4.
At this time, since selectively-grown tungsten 14 has a grain size of several thousands .ANG., undulations of about 1,000 .ANG. are formed on its surface. In addition, selective growth of tungsten is very sensitive to a surface condition of a substrate on which the tungsten is to be grown. Therefore, in consideration of difficulty in controlling a film thickness, in order to prevent electrical short-circuit which occurs when tungsten in one connection hole overflows and contacts tungsten selectively grown in an adjacent connection hole, an average grown film thickness of tungsten must be about 80% or less of a depth of the connection hole. Thereafter, as shown in FIG. 11D, a metal layer 17 is deposited by a normal sputtering method to form a wiring layer by normal lithography and etching.
In this method, the wiring layer 17 must sufficiently cover the tungsten 14 in the connection hole 4. However, since the aspect ratio is increased in a recess of the tungsten 14, the wiring layer 17 cannot have a sufficient film thickness, and therefore a wiring resistance is largely increased at this portion. In the worst case, disconnection occurs. Therefore, the tungsten selective growth method is not sufficient to form fine multi-layered wirings with a high yield and reliability. Furthermore, since connection holes having different depths are present as described above, the above problems become more serious.